1. Field of the Invention
The present invention relates to an oscillator circuit and a semiconductor memory device using the same, and to improvement of an oscillator circuit generating a clock signal for controlling, for example, a refresh operation.
2. Description of the Background Art
In the field of oscillator circuits generating a clock signal, particularly an oscillator circuit incorporated in a semiconductor integrated circuit, the demand for an oscillator circuit having the frequency of a clock signal altered according to a change in operating temperature is increasing. This demand is particularly appreciable for an oscillator circuit that generates a clock signal for controlling a refresh operation in, for example, a DRAM.
Because the data retaining time period in a memory cell of a DRAM becomes shorter due to increase in leakage current caused by a rise in operating temperature, a refresh operation must be carried out frequently, in other words, the refresh cycle must be shortened. However, a shorter refresh cycle will result in a greater number of refresh operations even at a low operating temperature, i.e. at ordinary temperature, to increase current consumption. This becomes a critical problem when a DRAM operative by a power supply of 5 V is operated by a low power supply of 3.3 V.
Therefore, an oscillator circuit generating a clock signal for controlling a refresh operation is desired having the oscillation frequency altered according to a change in temperature, so that the refresh cycle is lengthened when operating at ordinary temperature to decrease current consumption and the refresh cycle is shortened when operating at a high temperature to carry out a refresh operation reliably.
The foregoing will be described in detail with an oscillator circuit applied in a DRAM.
FIG. 22 is a block diagram showing an entire structure of a DRAM (Dynamic Random Access Memory).
Referring to FIG. 22, a DRAM includes a memory cell array 1, a RAS buffer 2, a CAS buffer 3, a WE buffer 4, a row address buffer 5, a row decoder 6, a word driver 7, a sense amplifier 8, a column address buffer 9, a column decoder 10, and an I/O circuit 11.
Memory cell array 1 includes a plurality of word lines, and a plurality of bit line pairs crossing the plurality of word lines, and a plurality of memory cells disposed in the proximity of the crossings thereof. Each memory cell includes a capacitor for storing data, and an N channel transistor. An N channel transistor is connected between the capacitor and a bit line. The N channel transistor has its gate connected to a word line.
RAS buffer 2 receives an external row address strobe signal/RAS to generate an internal row address strobe signal/RAS1. CAS buffer 3 receives an external column address strobe signal/CAS to generate an internal column address strobe signal/CAS1. WE buffer 4 receives an external write enable signal/W to generate an internal write enable signal/WI.
In a general operation mode, row address buffer 5 receives an external row address signal ADD via a switch 17 and generates a row address signal in response to an internal row address strobe signal/RAS1. Row decoder 6 responds to a row address signal from row address buffer 5 to select one of the plurality of word lines in memory cell array 1. Word driver 7 drives the word line selected by row decoder 6 to a predetermined voltage. As a result, data from each of the plurality of memory cells connected to the selected word line is read out to a corresponding bit line. Data read out on each bit line is amplified by a sense amplifier 8.
Column address buffer 9 receives an external column address signal ADD to generate a column address signal in response to an internal column address strobe signal/CAS1. Column decoder 10 responds to a column address signal to select one of the plurality of bit line pairs. As a result, the selected bit line pair is connected to an input/output line pair 12.
In a writing operation, an externally applied input data D is provided to an input/output line pair 12 via I/O circuit 11. In a reading operation, data on an input/output line pair 12 is output as data D via I/O circuit 11.
A DRAM has data stored by providing charge to a capacitor. It is therefore necessary to rewrite data within a constant time period to retain the stored data.
Therefore, this DRAM further includes a self refresh switching circuit 13, an internal address generation circuit 14, a ring oscillator 15, and a frequency divider 16.
Self refresh switching circuit 13 responds to internal row address strobe signal/RAS1 and internal column address strobe signal/CAS1 to generate a self refresh signal SREF indicating that a refresh operation is carried out internally and automatically. Internal address generation circuit 14 is activated in response to self refresh signal SREF, and sequentially generates a refresh address signal indicating a refresh address in response to internal row address strobe signal/RAS1.
Referring to FIG. 23, ring oscillator 15 includes inverters I1-I7 of an odd number of stages connected in a ring manner for generating a clock signal .phi..sub.CP of a constant cycle. Frequency divider 16 includes a plurality of counters C1-Cn to divide a frequency of clock signal .phi..sub.CP for generating a refresh enable signal REFE. RAS buffer 2 further responds to a refresh enable signal REFE to generate internal row address strobe signal/RAS1.
A self refresh operation of this DRAM will be described hereinafter with reference to the timing chart of FIG. 24.
When external row address strobe signal/RAS is brought to a L level (logical low) at time t1 after the fall of external column address strobe signal/CAS to a L level (/CAS before/RAS refresh cycle), self refresh switching circuit 13 pulls self refresh signal SREF to a H level (logical high) at time t2, i.e. at an elapse of a predetermined time period from time t1. This causes internal address generation circuit 14 and ring oscillator 15 to be activated. As a result, ring oscillator 15 generates a clock signal .phi..sub.CP. Frequency divider 16 frequency-divides clock signal .phi..sub.CP for generating a refresh enable signal REFE. RAS buffer 2 responds to refresh enable signal REFE for rendering internal row address strobe signal/RAS1 to a H level and a L level alternately. Internal address generation circuit 14 responds to internal row address strobe signal/RAS1 for sequentially generating a refresh address signal.
Row address buffer 5 responds to the fall of external row address strobe signal/RAS1 for sequentially providing to row decoder 6 a refresh address signal from internal address generation circuit 14. Row decoder 6 responds to a refresh address signal to sequentially select a word line in memory cell array 1. Word driver 7 drives the word line selected by row decoder 6 to a predetermined voltage. This causes data to be read out from each of the plurality of memory cells connected to the selected word line into a corresponding bit line. The data read out from each bit line is amplified by sense amplifier 8. This amplified data is written again into the read out memory cell via a bit line. Thus, data in a plurality of memory cells connected to a selected word line are refreshed.
Execution of such a self refresh operation of reading out data from a memory cell and then writing data into the memory cell again expends current. Therefore, current consumption increases as the number of refresh operations per unit time is increased.
In order to minimize current consumption, the cycle of an internal row address strobe signal/RAS1 generated according to ring oscillator 15 and frequency divider 16 is made as long as possible insofar as the data retention of a memory cell is not degraded. Because it is generally difficult to continuously alter the frequency dividing rate of frequency divider 16, the oscillation cycle of ring oscillator 15 is set as long as possible.
If the data retaining performance is superior, the cycle of internal row address strobe signal/RAS1 can be lengthened extremely. If the data retaining performance is poor, the cycle must be shortened. In this case, the number of refresh operations executed within a predetermined time is increased to increase operating current.
Data retainability is determined according to various factors such as the structure of a memory cell, conditions in the manufacturing process, the capacity of the capacitor, and the sensitivity of the sense amplifier. Therefore, appropriate adjustment is carried out for each DRAM to optimize the cycle of an internal row address strobe signal/RAS.
In the above-described DRAM, RAS buffer 2, row address buffer 5, row decoder 6, word driver 7, sense amplifier 8, sense refresh switching circuit 13, internal address generation circuit 14, frequency divider 16, and ring oscillator 15 form refresh means for carrying out a refresh operation of a memory cell.
In the above-described conventional DRAM, the cycle of internal row address strobe signal/RAS1 is determined by ring oscillator 15. Therefore, when the operating temperature becomes high to result in a greater resistance of transistors forming inverters I1-I7, the oscillation cycle is lengthened. There was a problem that the time period from the fall to the next fall of a refresh enable signal REFE (referred to as a "self refresh cycle" hereinafter) when self refresh signal SREF attains a H level becomes longer as the operating temperature rises.
The data retaining time period of a memory cell is apt to be shortened due to increase in subthreshold current in a memory cell or leakage current in a PN junction as the operating temperature rises. It was therefore necessary to set the refresh cycle slightly shorter to compensate for the worst case at high temperature in order to ensure data retention. Thus, there was a problem that an excessive number of refresh operations is carried out at ordinary temperature to increase current consumption.
An oscillator circuit solving such a problem is disclosed in Japanese Patent Laying-Open No. 63-100698, for example.
FIG. 25 is a circuit diagram showing a structure of this oscillator circuit.
Referring to FIG. 25, an oscillator circuit includes three stages of inverters connected in a ring manner, and a thermistor S for feeding back the output of the inverter of the last stage to the inverter of the first stage. Each inverter includes P channel MOS transistors Q.sub.P1, Q.sub.P2 and Q.sub.P3, and N channel MOS transistors Q.sub.N1, Q.sub.N2, and Q.sub.N3.
Thermistor S is reduced in resistance as the temperature rises. Therefore, the charging/discharging operation with respect to the gates of transistors Q.sub.P1 and Q.sub.N1 is carried out more rapidly as the temperature rises to result in a shorter oscillation cycle. By using such an oscillator circuit for a refresh operation in a DRAM, the refresh cycle can be shortened as the operating temperature rises.
Similarly, a circuit is disclosed in Japanese Patent Laying-Open No. 4-192178 that has the refresh cycle shortened as the operating temperature rises by using a thermistor.
It is logically possible to alter the refresh cycle in response to a change in temperature according to the circuit. However, a substance decreased in resistance as the temperature rises, i.e. a material having a negative temperature coefficient, is seldom found in the natural world. Furthermore, even if there is a material having a negative temperature coefficient, the absolute value thereof is too small to alter sufficiently the refresh cycle in response to variation in temperature.
Japanese Patent Laying-Open No. 4-344387 discloses a circuit with a leak monitor having characteristics identical to that of a memory cell for initiating a refresh operation when the voltage of the storage node in the leak monitor becomes lower than a predetermined reference voltage. Charge storage in the leak monitor is rapidly lost as the operating temperature rises, similar to a normal memory cell. Therefore, a refresh operation is carried out appropriately in response to a shift in temperature.
Japanese Patent Laying-Open No. 61-139995 discloses a device that provides charge appropriately to the capacitor in the above-described leak monitor. A refresh operation is reliably initiated before data in a proper memory cell is lost.
Although a refresh operation is executed appropriately in response to a change in the operating temperature in the devices of the above-described publications, it is extremely difficult to determine the reference voltage of the storage node by which a reference operation is to be initiated. It is also difficult to respond to a rapid change in temperature since a refresh operation is executed only after the voltage of the storage node becomes lower than the reference voltage.
As mentioned above, it is required that ring oscillator 15 has a long oscillation cycle with low power consumption. In order to obtain an oscillation cycle of several .mu.s, the on resistance of transistors forming each inverter in ring oscillator 15 must be set to approximately 1 M.OMEGA.. To realize such an on resistance, these transistors must have a gate length of tens of .mu.m. Therefore, the gate capacitance per transistor is approximately l pF.
In the case of ring oscillator 15 formed of 7 stages of inverters shown in FIG. 23, a current i flowing within a time period of several .mu.s is represented by the following equation 1 when the power supply voltage V.sub.cc is 3 V. ##EQU1##
Thus, it was difficult to lengthen the oscillation cycle of a ring oscillator while suppressing current consumption.
FIG. 26 is a circuit diagram showing a structure of an oscillator circuit disclosed in Japanese Patent Laying-Open No. 63-276316. Referring to FIG. 26, this oscillator circuit includes a reference voltage generation circuit 18 for generating two reference voltages, and an oscillator unit 19 for generating a clock signal .phi..sub.CP of a predetermined cycle. Oscillator unit 19 is formed by a ring oscillator including three inverters 191, 192 and 193.
According to this oscillator circuit, a voltage of power supply voltage V.sub.cc less the threshold voltage of P channel MOS transistor Q.sub.P4 in reference voltage generation circuit 18 is applied to the gates of P channel MOS transistors Q.sub.P5 -Q.sub.P7 in inverters 191-193, and a voltage of the ground voltage plus the threshold voltage of N channel MOS transistor Q.sub.N4 is applied to the gates of N channel MOS transistors Q.sub.N5 -Q.sub.N7. Therefore, a clock signal .phi..sub.CP of a predetermined cycle is constantly generated despite a change in the power supply voltage V.sub.cc. The object of this oscillator circuit is to stabilize the oscillation cycle of a ring oscillator, and differs from the objects of the invention of the present application described in the following.